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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2002 analog devices, inc. all rights reserved. AD8351 low distortion differential rf/if amplifier preliminary technical data preliminary technical data features ? db bandwidth of 2.2 ghz for a v = 12 db single resistor programmable gain 0 db a v 26 db differential interface low noise input stage 2.7 nv/ hz @ a v = 10 db low harmonic distortion ?9 dbc second @ 70 mhz ?1 dbc third @ 70 mhz oip3 of 31 dbm @ 70 mhz single-supply operation: 3 v to 5.5 v low power dissipation 28 ma @ 5 v adjustable output common-mode voltage fast settling and overdrive recovery slew rate of 13,000 v/ sec power-down capability 10-lead msop package applications differential adc driver single-ended to differential conversion if sampling receivers rf/if gain blocks saw filter interfacing functional block diagram v ocm vpos ophi oplo comm pwup rgp1 inhi inlo rgp2 AD8351 bias cell general description the AD8351 is a low cost differential amplifier useful in rf and if applications up to 2.2 ghz. the voltage gain can be set from unity to 26 db using a single external gain resistor. the AD8351 provides a nominal 150 ? differential output impedance. the excellent distortion performance and low-noise characteristics of this device allow for a wide range of applications. the AD8351 is designed to satisfy the demanding performance requirements of communications transceiver applications. the device can be used as a general-purpose gain block, an adc driver, 0510 15 20 25 30 35 2 3 + rg AD8351 100nf 100nf 25 25 ad6645 14 - bit adc inhi inlo 200 AD8351 AD8351 with 10 db of g ain driving the ad6645 (r l = 1k ) analog input: 70mhz encode : 80mhz snr : 69.1 db fund : ?.1 dbfs hd2 : ?8.5 dbc hd3 : ?0.7 dbc thd : ?5.9 dbc sfdr : 78.2 dbc 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?20 ?00 ?30 ?10 and high speed data interface driver, among other functions. the AD8351 can also be used as a single-ended to differential amplifier with similar distortion products as in the differential configuration. the exceptionally good distortion performance makes the AD8351 an ideal solution for 12-bit and 14-bit if sampling receiver designs. fabricated in adi? high speed xfcb process, the high bandwidth of the AD8351 provides high frequency performance and low distortion. the quiescent current of the AD8351 is 28 ma typically. the AD8351 amplifier comes in a compact 10-lead msop package and will operate over the temperature range of ?0 c to +85 c. rev. pri
rev. pri ? AD8351?pecifications preliminary technical data (v s = 5 v, r l = 150 , r g = 110 (a v = 10 db), f = 70 mhz, t = 25 c, parameters specified differentially, unless otherwise noted.) parameter conditions min typ max unit dynamic performance ? db bandwidth gain = 6 db, v out 1.0 v p-p 3000 mhz gain = 12 db, v out 1.0 v p-p 2200 mhz gain = 18 db, v out 1.0 v p-p 600 mhz bandwidth for 0.1 db flatness 0 db gain 20 db, v out 1.0 v p-p 200 mhz bandwidth for 0.2 db flatness 0 db gain 20 db, v out 1.0 v p-p 400 mhz gain accuracy using 1% resistor for r g , 0 db a v 20 db 1db gain supply sensitivity v s 5% 0.08 db/v gain temperature sensitivity ?0 c to 85 c 3.9 mdb/ c slew rate r l = 1 k ? v out = 2 v step 13,000 v/ s r l = 150 ? , v s = 2 v step 7,500 v/ s settling time 1 v step to 1% <3 ns overdrive recovery time v in = 4 v to 0 v step, v out 10 mv <2 ns reverse isolation (s12) ?7 db input/output characteristics input common-mode voltage adjustment range 1.2 to 3.8 v max output voltage swing 1 db compressed 4.75 v p-p output common-mode offset 40 mv output common-mode drift ?0 c to 85 c 0.24 mv/ c output differential offset voltage 20 mv output differential offset drift ?0 c to 85 c 0.13 mv/ c input bias current 15 a input resistance 1 5k ? input capacitance 1 0.8 pf cmrr 43 db output resistance 1 150 ? output capacitance 1 0.8 pf power interface supply voltage 3 5.5 v pwup threshold 1.3 v pwup input bias current pwup at 5 v 100 a pwup at 0 v 25 a quiescent current 28 32 ma
rev. pri AD8351 ? preliminary technical data specifications parameter conditions min typ max unit noise/distortion 10 mhz second/third harmonic distortion 2 r l = 1 k ? , v out = 2 v p-p ?5/ ?3 dbc r l = 150 ? , v out = 2 v p-p ?6/ ?1 dbc third-order imd r l = 1 k ? , f1 = 9.5 mhz, f2 = 10.5 mhz, v out = 2 v p-p composite ?0 dbc r l = 150 ? , f1 = 9.5 mhz, f2 = 10.5 mhz, v out = 2 v p-p composite ?0 dbc output third-order intercept f1 = 9.5 mhz, f2 = 10.5 mhz 33 dbm noise spectral density (rti) 2.65 nv/ hz 1 db compression point 13.5 dbm 70 mhz second/third harmonic distortion 2 r l = 1 k ? , v out = 2 v p-p ?9/ ?1 dbc r l = 150 ? , v out = 2 v p-p ?5/ ?6 dbc third-order imd r l = 1 k ? , f1 = 69.5 mhz, f2 = 70.5 mhz, v out = 2 v p-p composite ?5 dbc r l = 150 ? , f1 = 69.5 mhz, f2 = 70.5 mhz, v out = 2 v p-p composite ?9 dbc output third-order intercept f1 = 69.5 mhz, f2 = 70.5 mhz 31 dbm noise spectral density (rti) 2.70 nv/ hz 1 db compression point 13.3 dbm 140 mhz second/third harmonic distortion 2 r l = 1 k ? , vout = 2 v p-p ?9/ ?9 dbc r l = 150 ? , vout = 2 v p-p ?4/?3 dbc third-order imd r l = 1 k ? , f1 = 139.5 mhz, f2 = 140.5 mhz, v out = 2 v p-p composite ?9 dbc r l = 150 ? , f1 = 139.5 mhz, f2 = 140.5 mhz, v out = 2 v p-p composite ?7 dbc output third-order intercept f1 = 139.5 mhz, f2 = 140.5 mhz 29 dbm noise spectral density (rti) 2.75 nv/ hz 1 db compression point 13 dbm 240 mhz second/third harmonic distortion 2 r l = 1 k ? , vout = 2 v p-p ?0/?6 dbc r l = 150 ? , vout = 2 v p-p ?6/?0 dbc third-order imd r l = 1 k ? , f1 = 239.5 mhz, f2 = 240.5 mhz, v out = 2 v p-p composite ?6 dbc r l = 150 ? , f1 = 239.5 mhz, f2 = 240.5 mhz, v out = 2 v p-p composite ?2 dbc output third-order intercept f1 = 239.5 mhz, f2 = 240.5 mhz 27 dbm noise spectral density (rti) 2.90 nv/ hz 1 db compression point 13 dbm notes 1 values are specified differentially. 2 see applications section of datasheet for single-ended to differential performance. (v s = 5 v, r l = 150 , r g = 110 (a v = 10 db), f = 70mhz, t = 25 c, parameters specified differentially, unless otherwise noted .)
preliminary technical data rev. pri ? AD8351 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8351 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* supply voltage v pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v pwup voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v pos internal power dissipation . . . . . . . . . . . . . . . . . . . . . 320 mw ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 c/w maximum junction temperature . . . . . . . . . . . . . . . . . 125 c operating temperature range . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration 1 AD8351 pwup rgp1 inhi inlo rgp2 v ocm vpos ophi oplo comm 2 3 4 5 10 9 8 7 6 top view (not to scale) ordering guide model temp. range package description package option branding AD8351arm ?0 c to +85 ct ube, 10-lead micro msop rm-10 da AD8351arm-reel7 7" tape and reel AD8351-eval evaluation board pin function descriptions pin no. name function 1p wup apply a positive voltage (1.3 v v pwup v pos ) to activate device. 2 rgp1 gain resistor input 1. 3 inhi balanced differential input. biased to midsupply, typically ac-coupled 4 inlo balanced differential input. biased to midsupply, typically ac-coupled. 5 rgp2 gain resistor input 2. 6 comm device common. connect to low impedance ground. 7 oplo balanced differential output. biased to vocm, typically ac-coupled. 8 ophi balanced differential output. biased to vocm, typically ac-coupled. 9 vpos positive supply voltage. 3 v to 5.5 v. 10 vocm voltage applied to this pin sets the common-mode voltage at both the input and output. typically decoupled to ground with a 0.1 f capacitor.
preliminary technical data rev. pri t ypical performance characteristics ? AD8351 frequency ?mhz 1 10000 gain ?db 0 10 100 1000 20 15 10 5 ? r g = 20 r g = 80 r g = 200 tpc 1. gain vs. frequency for a 150 ? differential load (a v = 6 db, 12 db, and 18 db) r g ? 35 10 10k gain ?db 25 15 5 ? ?0 100 1k 30 20 10 0 rl = open rl = 1k rl = 150 tpc 2. gain vs. gain resistor, r g (f = 100 mhz, r l = 150 k ? , 1 k ? and open) temperature ? c 10.75 ?0 110 gain (rl = 1k ) ?db 10.50 10.00 9.50 9.25 ?0 50 10.25 9.75 ?0 10 30 70 90 9.00 gain (rl = 150 ) ?db 10.50 10.00 9.50 9.25 10.25 9.75 tpc 3. gain vs. temperature at 100 mhz (a v = 10 db) (v s = 5 v, t = 25 c, unless otherwise noted.) frequency ?mhz 30 1 10000 gain ?db 5 10 100 1000 25 20 15 10 0 r g = 20 r g = 80 r g = 200 tpc 4. gain vs. frequency for a 1 k ? differential load (a v = 10 db, 18 db, and 26 db) frequency ?mhz 0.8 1 1000 gain flatness ?db 0.4 0 ?.4 ?.8 ?.0 10 100 0.6 0.2 ?.2 ?.6 0.5 0.1 ?.3 ?.7 ?.9 0.7 0.3 ?.1 ?.5 0.9 1.0 rl = 150 rl = 1k rl = 150 rl = 1k tpc 5. gain flatness vs. frequency (r l = 150 k ? and 1 k ? , a v =10 db) frequency ?mhz 0 1000 isolation ?db ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 100 200 300 400 500 600 700 800 900 tpc 6. isolation vs. frequency (a v = 10 db)
preliminary technical data rev. pri ? AD8351 frequency ?mhz 0 250 harmonic distortion (v pos = 5v) ?dbc ?0 ?0 ?0 ?0 ?0 ?0 ?0 25 50 75 100 125 150 175 200 225 ?00 ?5 ?5 ?5 ?5 ?5 ?5 ?05 ?15 harmonic distortion (v pos = 3v) ?dbc hd2 hd3 hd3 hd2 tpc 7. harmonic distortion vs. frequency for 2 v p-p into r l = 1 k ? (a v = 10 db, at 3 v and 5 v supplies) frequency ?mhz 0 250 harmonic distortion (v pos = 5v) ?dbc ?0 ?0 ?0 ?0 ?0 ?0 0 25 50 75 100 125 150 175 200 225 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 harmonic distortion (v pos = 3v) ?dbc ?0 ?0 ?00 ?10 hd3 hd2 hd2 hd3 tpc 8. harmonic distortion vs. frequency for 2 v p-p into r l = 150 ? (a v = 10 db, at 3 v and 5 v supplies) frequency ?mhz 0 250 noise spectral density ?nv/ hz 2.80 2.70 2.85 2.75 2.90 2.95 3.00 50 100 150 200 2.65 2.60 2.55 2.50 tpc 9. noise spectral density (rti) vs. frequency (rl = 150 ? , 5 v supply, a v = 10 db) frequency ?mhz 0 100 harmonic distortion ?dbc ?0 ?0 ?5 ?5 ?0 ?5 ?0 10 40 60 80 ?5 ?0 ?5 ?00 20 30 50 70 90 hd3 hd3 hd2 tpc 10. harmonic distortion vs. frequency for 2 v p-p into r l = 1 k ? using single-ended input (a v = 10 db) frequency ?mhz 0 100 harmonic distortion ?dbc ?0 ?0 ?5 ?5 ?0 ?5 ?0 10 40 60 80 ?5 ?0 ?5 ?00 20 30 50 70 90 hd2 hd3 tpc 11. harmonic distortion vs. frequency for 2 v p-p into rl = 150 ? using single-ended input (a v = 10 db) frequency ?mhz 0 250 2.80 2.70 2.85 2.75 2.90 2.95 3.00 50 100 150 200 2.65 2.60 2.55 2.50 noise spectral density ?nv/ hz tpc 12. noise spectral density (rti) vs. frequency (r l = 150 ? , 3 v supply, a v = 10 db)
preliminary technical data rev. pri AD8351 ? frequency ?mhz 0 250 8 4 10 6 12 14 16 25 50 75 100 125 150 175 200 225 2 0 output 1db compression ?dbm r l = 150 v pos = 5v r l = 1k r l = 150 v pos = 3v r l = 1k tpc 13. output compression point, p1 db, vs. frequency (r l = 150 ? and 1 k ? , a v = 10 db, at 3 v and 5 v supplies) gain resistor 0 1000 100 8 4 10 6 12 14 16 2 0 output 1db compression ?dbm v pos = 5v v pos = 3v tpc 14. output compression point, p1db, vs. rg (f = 100 mhz, r l = 150 ? , a v = 10 db, at 3 v and 5 v supplies) output 1db compression ?db 13.29 13.31 13.33 13.34 13.30 13.32 13.35 13.36 13.37 13.38 13.39 13.40 13.41 tpc 15. output compression point distribution (f = 70 mhz, r l = 150 ? , a v = 10 db) frequency ?mhz 0 250 ?0 ?5 ?5 ?0 ?5 ?0 25 50 75 100 125 150 175 200 225 third order imd ?dbc tpc 16. third-order intermodulation distortion vs. frequency for a 2 v p-p composite signal into r l = 1 k ? (a v = 10 db, at 5 v supplies) frequency ?mhz 0 250 ?0 ?5 ?5 ?0 ?5 ?0 25 50 75 100 125 150 175 200 225 third order imd ?dbc tpc 17. third-order intermodulation distortion vs. frequency for a 2 v p-p composite signal into rl = 150 ? (a v = 10 db, at 5 v supplies) third order intermodulation distortion ?dbc ?8.0 ?8.2 ?8.4 ?8.6 ?8.6 ?8.8 ?9.0 ?9.2 ?9.4 ?9.6 ?9.8 tpc 18. third-order intermodulation distortion distribution (f = 70 mhz, r l = 150 ? , a v = 10 db)
preliminary technical data rev. pri ? AD8351 frequency ?mhz 10 1000 100 2000 1000 2500 1500 3000 3500 4000 500 0 impedance magnitude ? 0 -25 -50 -75 -100 impedance phase ?deg tpc 19. input impedance vs. frequency frequency ?mhz 0 1000 100 120 100 130 110 140 150 160 mpedance magnitude ? 30 15 10 5 0 impedance phase ?deg 20 25 tpc 20. output impedance vs. frequency frequency ?mhz 0 250 ? ? ?0 ? ? 0 25 50 75 100 125 150 175 200 225 phase ?deg 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 group delay ?psec ?2 ?4 ?6 ?8 tpc 21. phase and group delay (a v = 10 db, at 5 v supplies) 10mhz 3ghz 3ghz 10mhz with 50 te rminations without te rminations 500mhz 500mhz tpc 22. input reflection coefficient vs. frequency (r s = r l = 100 ? with and without 50 ? terminations) 3ghz 10mhz 500mhz tpc 23. output reflection coefficient vs. frequency (r s = r l = 100 ? ) frequency ?mhz 80 20 0 1000 cmrr ?db 100 10 r l = 1k r l = 150 70 60 40 50 30 tpc 24. common-mode rejection ratio, cmrr (r s = 100 ? )
preliminary technical data rev. pri AD8351 ? time ?ns 15 25 ?.2 ?.6 0 ?.4 0.2 0.4 0.6 16 17 18 19 20 21 22 23 24 vo ltag e ?v 0pf 2pf 10pf 5pf tpc 25. transient response under capacitive loading (r l = 150 ? , c l = 0 pf, 2 pf, 5 pf, 10 pf) time ?ns 0 5.0 51015202 5303 540 output ?v 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 4.5 tpc 26. 2x output overdrive recovery (r l = 150 ? , a v = 10 db) time ?ns 050 3 5101 5202530354045 vo ltag e ?v 2 1 0 ? ? ? v out v in tpc 27. overdrive recovery using sinusoidal input waveform r l = 150 ? (a v = 10 db, at 5 v supplies) time ?ns 0 vo ltag e ?v 0.75 0.25 ?.5 ?.0 1.0 0.5 0 ?.25 ?.75 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 tpc 28. large signal transient response for a 1 v p-p output step (a v = 10 db, r ip = 25 ? ) time ?ns 015 5 36912 settling ?% 2 1 0 ? ? ? 3 4 ? ? tpc 29. 1% settling time for a 2 v p-p step (a v = 10 db, r l = 150 ? )
preliminary technical data rev. pri ?0 AD8351 basic concepts differential signaling is used in high performance signal chains where distortion performance, signal to noise ratio, and low power consumption is critical. differential circuits inherently provide improved common-mode rejection and harmonic distortion perfor- mance as well as better immunity to interference and ground noise. v ocm 10 vpos 9 ophi 8 oplo 7 comm 6 1 pwup rgp1 2 inhi 3 inlo 4 rgp2 5 r g ba lanced source r l a a 2a figure 1. differential circuit representation figure 1 illustrates the expected input and output waveforms for a typical application. usually the applied input waveform will be a balanced differential drive, where the signal applied to the inhi and inlo pins are equal in amplitude and differ in phase by 180 . in some applications, baluns may be used to transform a single-ended drive signal to a differential signal. the AD8351 may also be used to transform a single-ended signal to differential. gain adjustment the differential gain of the AD8351 is set using a single external resistor, r g , which is connected between pins 2 and 5. the gain can be set to any value between 0 db to 26 db using the resistor values specified in tpc 2, with common gain values provided in table i. the board traces used to connect the external gain resis- tor should be balanced and as short as possible to help prevent noise pickup and ensure balanced gain and stability. the low frequency voltage gain of the AD8351 can be modeled as: a rr rr rr r rr r v v v lg f l gl g lf g out in = () + + + + () () = 56 92 .. 4.6 19.5 39 where: r fi = 350 ? (internal) r l is the single-ended load resistance r g = gain setting resistor table i. gain resistor selection for common gain values. load resistance is specified as single-ended. gain, a v r g (r l = 75 ? )r g (r l = 500 ? ) 0 db 680 ? 2 k ? 6 db 200 ? 470 ? 10 db 100 ? 200 ? 20 db 22 ? 43 ? common-mode adjustment the output common-mode voltage level is the dc offset voltage present at each of the differential outputs. the ac signals are of equal amplitude with a 180 phase difference but are centered at the same common-mode voltage level. the common-mode output voltage level can be adjusted from 1.2 v to 3.8 v by driving the desired voltage level into the vocm pin as illus- trated in figure 2. v ocm 10 vpos 9 ophi 8 oplo 7 comm 6 1 pwup rgp1 2 inhi 3 inlo 4 rgp2 5 r g ba lanced source r l 0.1 f v s v ocm 1.2v to 3.8v c decl 0.1 f figure 2. common-mode adjustment input and output matching the AD8351 provides a moderately high differential input impedance of 5 k ? . in practical applications, the input of the AD8351 will be terminated to a lower impedance to provide an impedance match to the driving source as depicted in figure 3. the terminating resistor, r t , should be as close as possible to the input pins in order to minimize reflections due to imped- ance mismatch. the 150 ? output impedance may need to be transformed to provide the desired output match to a given load. matching components can be calculated using a smith chart or by using a resonant approach to determine the match- ing network that results in a complex conjugate match. the input and output impedances and reflection coefficients are provided in tpcs 19, 20, 22, and 23. for additional informa- tion on reactive matching to differential sources and loads, refer to the applications section of the ad8350 data sheet. figure 3 illustrates a saw (surface acoustic wave) filter inter- face. many saw filters are inherently differential allowing for a low loss output match. in this example, the saw filter requires a 50 ? source impedance in order to provide the desired center frequency and q. the series l shunt c output network provides a 150 ? to 50 ? impedance transformation at the desired frequency of operation. the impedance transformation is illustrated on a smith chart in figure 4. it is possible to drive a single-ended saw filter simply by con- necting the unused output to ground using the appropriate terminating resistance. the overall gain of the system will be reduced by 6 db due to the fact that only half of the signal will be available to the input of the saw filter. ba lanced source r s r s r s = r t r t r t 0.1 f 0.1 f r g 0.1 f 0.1 f 150 c p 8pf l s 27nf l s 27nf 50 190mhz saw vpos figure 3. example of differential saw filter interface (f c = 190 mhz)
preliminary technical data rev. pri AD8351 ?1 200 0 50 150 series l shunt c 500 100 50 25 10 200 100 500 50 25 10 figure 4. smith chart representation of saw filter output matching network 50 50 AD8351 r g 0.1 f 25 r f 0.1 f 0.1 f r l 0.1 f figure 5. single-ended application single-ended to differential operation the AD8351 can easily be configured as a single-ended to differ- ential gain block, as illustrated in figure 5. the input signal is ac-coupled and applied to the inhi input. the unused input is ac-coupled to ground. the values of c1 through c4 should be selected such that their reactances are negligible at the desired frequency of operation. to balance the outputs an external feed- back resistor, r f , is required. to select the gain resistor and the feedback resistor refer to figures 6a and 6b. from figure 6a, select an r g for the required db gain at a given load. next, select from figure 6b an r f resistor for the selected r g and load. even though the differential balance is not perfect under these conditions, the distortion performance is still impressive. tpcs 10 and 11 show the second and third harmonic distortion perfor- mance when driving the input of the AD8351 using a single-ended 50 ? source. r g ? 0 1000 gain ?db 10 0 15 5 35 20 25 30 100 r l = 500 r l = 1000 r l = 150 figure 6a. gain selection r g ? 0 1000 r f ? 2000 0 3000 1000 7000 4000 5000 6000 100 r l = 150 r l = 1000 r l = 500 figure 6b. feedback resistor selection adc driving the circuit in figure 7 represents a simplified front end of the AD8351 driving the ad6645 a 14-bit, 105 msps a/d converter. for optimum performance, the ad6645 and the AD8351 are driven differentially. the resistors r1 and r2 present a 50 ? differential input impedance to the source with r3 and r4 pro- viding isolation from the a/d input. the gain setting resistor for the AD8351 is r g . the ad6645 presents a 1 k ? differential load to the AD8351 and requires a 2.2 v p-p differential signal between ain and ?in for a full-scale output. this AD8351 circuit then provides the gain, isolation, and source matching for the ad6645. the AD8351 also provides a balanced input, not provided by the balun, to the ad6645, which is essential for second-order cancellation. the signal generator is bipolar, cen- tered around ground. connecting the vocm pin (10) of the AD8351 to the vref pin of the ad6645 sets the common-mode output voltage of the AD8351 at 2.4 v. this voltage is bypassed with a .1 f capacitor. increasing the gain of the AD8351 will increase the system noise and thus decrease the snr but will not significantly affect the distortion. the circuit in figure 7 can provide sfdr performance of better than ?0 dbc with a 10 mhz i nput, and ?0 dbc with a 70 mhz input at a gain of 10 db. ba lance 50 source 25 100nf 25 100nf AD8351 inhi inlo r g ophi oplo v ocm 25 25 digital out ad6645 ain ain vref figure 7. adc driving application using differential input the circuit of figure 8 represents a single-ended input to differen tial output configuration of the AD8351 driving the ad6645. in this case, r1 provides the input impedance. rg is the gain setting resistor. the resistor rf is required to balance the output voltages required for second-order cancellation by the ad6645 and can be selected using a chart. (see the single-ended to differential operation section.) the circuit depicted in figure 8 can provide sfdr performance of better than ?0 dbc with a 10 mhz input and ?7 dbc with a 70 mhz input.
preliminary technical data rev. pri ?2 AD8351 single ended 50 source r1 50 100nf 25 100nf AD8351 inhi inlo r g ophi oplo v ocm 25 25 digital out ad6645 ain ain vref 100nf r f figure 8. adc driving application using single-ended input analog multiplexing the AD8351 can be used as an analog multiplexer in applications where it is desirable to select multiple high speed signals. the isolation of each device when in a disabled state (pwup pin pulled low) is about 60 dbc for the maximum input level of 0.5 v p-p out to 100 mhz. the low output noise spectral density allows for a simple implementation as depicted in figure 9. the pwup inter- face can be easily driven using most standard logic interfaces. by using an n-bit digital interface, up to n devices can be controlled. output loading effects and noise need to be considered when using a large number of input signal paths. each disabled AD8351 pre- sents approximately a 700 ? load in parallel with the 150 ? output source impedance of the enabled device. as the load increases due to the addition of n devices, the distortion performance will degrade due to the heavier loading. distortion better than ?0 dbc can be achieved with four devices muxed into a 1 k ? load for signal fre- quencies up to 70 mhz. AD8351 inhi r g rpg1 rgp2 inlo signal input 1 oplo ophi bit 1 pwup AD8351 inhi r g rpg1 rgp2 inlo signal input 2 oplo ophi bit 2 pwup AD8351 inhi r g rpg1 rgp2 inlo signal input n oplo ophi bit n pwup mux output load n-bit digital interface figure 9. using several AD8351s to form an n-channel analog mux i/o capacitive loading i nput or output direct capacitive loading greater than a few pico- farads can result in excessive peaking and or oscillation outside the pass band. this results from the package and bond wire induc- tance resonating in parallel with the input/output capacitance of the device and the associated coupling that results internally through the ground inductance. for low resistive load or source resistance, the effective q is lower, and higher relative capaci- tance termination(s) can be allowed before oscillation or excessive peaking occurs. these effects can be eliminated by adding series input resistors (rip) for high source capacitance, or series output resistors (rop) for high load capacitance. generally less than 25 ? is all that is required for i/o capacitive loading greater than ~2 pf. the higher the c, the smaller the r parasitic suppression resistor required. in addition, rip also helps to reduce low gain in-band peaking, especially for light resistive loads. AD8351 r l 1k c stray c stray r ip r ip r g r op r op c l c l figure 10. input and output parasitic suppression resistors, rip and rop, used to suppress capacitive loading effects due to package parasitic capacitance on the r g ports, high r g values (low gain) cause high ac-peaking inside the pass band, resulting in poor settling in the time domain. as an example, when driving a 1 k ? load, using 25 ? for rip reduces the peaking by ~7 db for rg equal to 200 ? (a v = 10 db). see figure 11. frequency ?mhz 10 10k 20log(a v ) ?db 10 0 15 5 25 20 100 no r ip r ip = 25 1k figure 11. reducing gain peaking with parasitic suppressing resistors (rip = 25 ? , r l = 1 k ? )
preliminary technical data rev. pri AD8351 ?3 it is important to ensure that all i/o, ground, and r g port traces be kept as short as possible. in addition, it is required that the ground plane be removed from under the package. due to the inverse relationship between the gain of the device and the value of the r g resistor, any parasitic capacitance on the r g ports can result in gain-peaking at high frequencies. following the precau- tions outlined in figure 12 will help to reduce parasitic board capacitance, thus both extending the devices bandwidth and reducing potential peaking or oscillation. coplanar w a veguide or strip 2 1 3 4 5 9 10 8 7 6 r t r ip r t r ip r g r op r op hi-z agnd agnd figure 12. general description of recommended board layout for high-z load conditions transmission line effects as noted above, stray transmission line-capacitance, in combi- nation with package parasitics, can potentially form a resonant circuit at high frequencies resulting in excessive gain-peaking. rf transmission lines connecting the input and output networks should be designed such that stray capacitance is minimized. the output single-ended source impedance of the AD8351 is dynamically set to a nominal value of 75 ? . therefore, for a matched load termination the characteristic impedance of the output transmission lines should be designed to be 75 ? . in many situations the final load impedance may be relatively high, greater than 1 k ? . it is suggested that the board be designed as described in figure 12 for high impedance load conditions. in most practical board designs this requires that the printed- circuit board traces be dimensioned to a small width (~5 mils) and that the underlying and adjacent ground-planes are far enough away to minimize capacitance. typically the driving source impedance into the device will be low and terminating resistors will be used to prevent input reflec- tions. t he transmission line should be designed to have the appropriate characteristic impedance in the low-z region. the high impedance environment between the terminating resistors and device input pins should not have ground planes under- neath or near the signal traces. small parasitic suppressing resistors may be necessary at the device input pins to help desensitize (?e-q? the resonant effects of the device bond wires and surrounding parasitic board capacitance. typically 25 ? series resistors (size 0402) adequately ?e-q?the input system with- out a significant decrease in ac performance. figure 13 illustrates the value of adding input and output series resistors to help desensitize the resonant effects of board parasitics. overshoot and undershoot can be significantly reduced with the simple addition of rip and rop. time ?ns 04 vo ltag e ?v ?.5 ?.5 0 ?.0 1.5 0.5 13 1.0 2 r ip = r op = 25 no r ip or r op r op = 25 figure 13. step response characteristics with and with- out input and output parasitic suppression resistors characterization setup the test circuit used for 150 ? and 1 k ? load testing is provided in figure 14. the evaluation board uses balun transformers to simplify interfacing to single-ended test equipment. balun effects need to be removed from the measurements in order to accu- rately characterize the performance of the device at frequencies exceeding 1 ghz. the output l-pad matching networks provide a broadband impedance match with minimum insertion loss. the input lines are terminated with 50 ? resistors for input impedance matching. the power loss associated with these networks needs to be accounted for when attempting to measure the gain of the device. the required resistor values and the appropriate inser- tion loss and correction factors used to assess the voltage gain are provided in table i. table i. load conditions specified differentially conversion total factor load insertion 20 log (s21) condition r1 r2 loss to 20 log (a v ) 150 ? 43.2 ? 86.6 ? 5.8 db +7.6 db 1 k ? 475 ? 52.3 ? 15.9 db +25.9 db ba lanced source r s 50 0.1nf 0.1nf 100nf r load r s 50 r t 50 r t 50 50 cable 50 cable AD8351 dut r1 100nf 50 cable 50 cable r1 r2 r2 50 50 50 test equipment figure 14. test circuit
preliminary technical data rev. pri ?4 AD8351 evaluation board an evaluation board is available for experimentation. various parameters such as gain, common-mode level, and input and output network configurations can be modified through minor resistor changes. the schematic and evaluation board artwork are presented in figures 15, 16, and 17. 2 1 3 4 5 9 10 8 7 6 pwup vocm rgp1 vpos inhi ophi inlo oplo rgp2 comm AD8351 10 pin soic r2 24.9 r1 100 r7 0 r5 0 r8 0 r4 24.9 r3 open r12 0 j1 rf_in+ j2 rf_in r15 0 r16 0 c6 100nf c7 100nf r10 61.9 t2 1:1 etc1-1-13 ( macom) r14 0 r13 open r11 61.9 r9 61.9 j3 rf_out+ j4 rf_out c3 0.1 f r6 open r17 0 c2 100nf agnd vpos enbl vcom vpos acom p1 r18 0 w1 c4 100nf c4 100nf t1 1:1 etc1-1-13 ( macom) c10 100nf c9 100nf t3 1:1 etc1-1-13 ( macom) j5 test in2 t4 1:1 etc1-1-13 ( macom) j6 test out2 figure 15. evaluation board schematic figure 16. component side layout figure 17. component side silkscreen.
preliminary technical data rev. pri AD8351 ?5 table ii. evaluation board configuration options component function default condition p1-1, p1?, supply and ground pins not applicable vpos, agnd p1? common-mode offset pin. allows for monitoring or adjustment of the not applicable output common-mode voltage. w1, r7, p1?, r15, r16 device enable. configured such that switch w1 disables device when pin 1 w1 = installed is set to ground. device can be disabled remotely using pin 4 of header p1. r7 = 0 ? (size 0603) r17 = r18 = 0 ? (size 0603) r2, r3, r4, r5, r8, r12, input interface. r3 and r12 are used to ground one side of the differential r2 = r4 = 24.9 ? (size 0805) t1, c4, c5 drive interface for single-ended applications. t1 is a 1-to-1 impedance ratio r3 = open (size 0603) balun used to transform a single-ended input into a balanced differential r5 = r8 = r12 = 0 ? signal. r2 and r4 are used to provide a differential 50 ? input-termination. (size 0603) r5 and r8 can be increased to reduce gain peaking when driving from a high c4 = c5 = 10 0 nf (size 0603) source impedance. the 50 ? termination provides an insertion loss of 6 db. t1 = macom tm etc1-1-13 c4 and c5 are used to provide ac-coupling. r9, r10, r11, r13, r14, output interface. r13 and r14 are used to ground one side of the differential r9 = r10 = 61.9 ? (size 0603) r15, r16, t2, c6, c7 output interface for single-ended applications. t2 is a 1-to-1 impedance ratio r11 = 61.9 ? (size 0603) balun used to transform a balanced differential signal into a single-ended r13 = open (size 0603) signal. r9, r10, and r11 are provided for generic placement of matching r14 = 0 ? (size 0603) components. r15 and r16 allow additional output series resistance when c6 = c7 = 100 nf (size 0603) driving capacitive loads. the evaluation board is configured to provide a t2 = macom etc1-1-13 150 ? to 50 ? impedance transformation with an insertion loss of 9.9 db. c3 and c4 are used to provide ac-coupling. r1 gain setting resistor. resistor r1 is used to set the gain of the device. r1 = 100 ? (size 0603) refer to tpc 2 when selecting gain resistor. when r1 is 100 ? , the overall system-gain of the evaluation board will be approximately ? db. c2 power supply decoupling. the supply decoupling consists of a 100 nf c2 = 100 nf (size 0805) capacitor to ground. r6, c3, p1-3 common-mode offset adjustment. used to trim common-mode output r6 = 0 ? (size 0603) level. by applying a voltage to pin 3 of header p1, the output common- c3 = 0.1 f (size 0805) mode voltage can be directly adjusted. typically decoupled to ground using a 0.1 f capacitor. t 3, t 4, c 9, c1 0 calibration networks. calibration path provided to allow for compensation t3 = t4 = m acom of the insertion loss of the baluns and the reactance of the coupling capacitors. etc1-1-13 c9 = c10 = 100 nf (size 0603)
preliminary technical data rev. pri c03145e0e11/02(pri) printed in u.s.a. e16e AD8351 outline dimensions 10-lead msop package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.40 8 0 0.15 0 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 compliant to jedec standards mo-187ba coplanarity 0.10

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